// -*- mode:c++ -*-

// Copyright (c) 2009 The University of Edinburgh
// Copyright (c) 2021 IBM Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'sd' : 'int64_t',
    'ud' : 'uint64_t',
    'sf' : 'float',
    'df' : 'double'
}};

def operands {{
    # General Purpose Integer Reg Operands
    'Rs': IntRegOp('ud', 'RS', 'IsInteger', 1),
    'Ra': IntRegOp('ud', 'RA', 'IsInteger', 2),
    'Rb': IntRegOp('ud', 'RB', 'IsInteger', 3),
    'Rc': IntRegOp('ud', 'RC', 'IsInteger', 4),
    'Rt': IntRegOp('ud', 'RT', 'IsInteger', 5),

    # General Purpose Floating Point Reg Operands
    'Fa': FloatRegOp('df', 'FRA', 'IsFloating', 1),
    'Fb': FloatRegOp('df', 'FRB', 'IsFloating', 2),
    'Fc': FloatRegOp('df', 'FRC', 'IsFloating', 3),
    'Fs': FloatRegOp('df', 'FRS', 'IsFloating', 4),
    'Ft': FloatRegOp('df', 'FRT', 'IsFloating', 5),

    # Memory Operand
    'Mem': MemOp('ud', None, (None, 'IsLoad', 'IsStore'), 8),

    # Program counter and next
    'CIA': PCStateOp('ud', 'pc', (None, None, 'IsControl'), 9),
    'NIA': PCStateOp('ud', 'npc', (None, None, 'IsControl'), 9),

    # Control registers
    'CR': IntRegOp('uw', 'int_reg::Cr', 'IsInteger', 9),
    'LR': IntRegOp('ud', 'int_reg::Lr', 'IsInteger', 9),
    'CTR': IntRegOp('ud', 'int_reg::Ctr', 'IsInteger', 9),
    'TAR': IntRegOp('ud', 'int_reg::Tar', 'IsInteger', 9),
    'XER': IntRegOp('uw', 'int_reg::Xer', 'IsInteger', 9),
    'MSR': IntRegOp('ud', 'int_reg::Msr', 'IsInteger', 9),

    # Setting as IntReg so things are stored as an integer, not double
    'FPSCR': IntRegOp('uw', 'int_reg::Fpscr', 'IsFloating', 9),

    # Registers for linked loads and stores
    'Rsv': IntRegOp('uw', 'int_reg::Rsv', 'IsInteger', 9),
    'RsvLen': IntRegOp('uw', 'int_reg::RsvLen', 'IsInteger', 9),
    'RsvAddr': IntRegOp('ud', 'int_reg::RsvAddr', 'IsInteger', 9),
}};
